UVM based Risc-V FPU verification environment
A SystemVerilog DPI wrapper integrates FPU-V into the UVM scoreboard to evaluate UUT’s outputs
This wrapper uses a random number generator to randomize input operands and incorporates corner cases.
FEVER was first used for verification of our FAUST FPU as a part of EPAC 1.0 before tape-out
for our next tape-out of faust in epac 1.5 we added additional features in fever
